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For memory, check the bus switch. And the T3 torus | 167 comments | Create New Account

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For memory, check the bus switch. And the T3 torus

Authored by: jesse on Monday, April 08 2013 @ 05:18 AM EDT

Used for every multi-cpu Cray system until the T3.

The t3 torus memory fabric provided both memory and application use for access
to small nodes - CPU + memory. The torus provided I/O via "special
nodes" that handled input/putput (T3E). (application nodes had 4 cpus, I/O
nodes replaced two cpus for I/O interfaces). Early 1980s. The first T3 (T3D)
depended on a host cray for I/O.

Error detection and correction at all levels.

Even the Cray host itself treated memory as a fabric The YMP-8/128 used a bus
switch (8 cpus with 4 memory channels each), memory was treated like a disk - a
fault would cause the memory to be remapped, with previous data copied (via ECC)
to prevent aborts. The error would be logged, and hardware engineers would then
replace the memory board during scheduled downtime.(My date was 1991, but the
hardware was created late 1980s)

[ Reply to This | Parent | # ]

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