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The description section of the patent describes somethng else | 661 comments | Create New Account
Comments belong to whoever posts them. Please notify us of inappropriate comments.
The description section of the patent describes somethng else
Authored by: bugstomper on Thursday, March 28 2013 @ 10:24 PM EDT
I could not bring myself to spend enough time reading the description section of
the patent to fully understand it, but it did seem that it describes an
alternate representation of floating point that is not IEEE 754-1985 compliant.
Well, while typing this I looked at it again to clear up some confusion. That's
some wasted minutes of my life that I will never get back. The description
section goes into detail about an alternate format for floating point
representation that is not IEEE 754 compliant, but has the following
characteristics: The representation of fp numbers in RAM is the same number of
bits size as IEEE 754. The meaning of the bits varies according to a mode. One
mode is the same as IEEE 754. There are another three modes, and when they are
used the mantissa has fewer bits and the other bits are used to indicate some
things about accuracy/underflow/overflow. The registers in the FPU have a
different format which requires them to have more bits so that they can hold all
the information of double precision IEEE format plus the extra bits used by the
other modes. I fail to see how one would use this in practice given that the RAM
representation does not tell you which of the four modes has been used to store
the number.

Thus this patent's Description section describes a non-standard format for
floating point numbers and the corresponding hardware for processing them in an
FPU. With that format and that processing there is not the problem you would get
by always rounding IEEE standard floating point numbers before computation.

If that is what the claims were about, there would be no problem with
infringement by any existing OS or computer, as nobody implements the floating
point format that is described.

However, Claim 1 mentions none of that. It pulls out four steps that can be used
to describe any processing of a floating point number that rounds before doing
other computations. The processing of the format in the Description does a step
that can be called "rounding" after a number is converted from the RAM
format to the format used by the FPU. Nobody would do that as a general step
with IEEE standard floating point numbers, but you might have some specific
computation you want to do in which you round a number before you continue with
the calculations. Claim 1 doesn't make that distinction - It doesn't say that it
claims a floating point processor that rounds values as a first step before
performing calculations. It claims doing anything with a floating point number
which includes loading it into a register and rounding it before doing a
calculation, even if you do not always do that for all your floating point
calculations.

There appears to be a complete disconnect between the claims and the Description
such that the claims are left being written to some very broad operations on
purely abstract numbers.

[ Reply to This | Parent | # ]

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