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| Authored by: SpaceLifeForm on Saturday, March 30 2013 @ 12:51 AM EDT |
| Somewhere in those machine
instruction codes
are bits that can tell you how the
raw data bits
are to be interpreted.
That is ultimately is what it gets
down to.
It is logic.
And logic just exists, only to be
applied, not
patented.
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You are being MICROattacked, from various angles, in a SOFT manner. [ Reply to This | Parent | # ]
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- Indeed so - Authored by: Anonymous on Saturday, March 30 2013 @ 06:30 PM EDT
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| Authored by: mtew on Saturday, March 30 2013 @ 02:16 AM EDT |
...in many cases the engineer does not have the last word so
the less than perfect understanding of some non-technical
lawyer prevails. It may even be being deliberately
obfuscated.
It also depends on the hardware implementation. For
example, the VAX architecture did have four different
floating point formats designated D, F, G and H. The Intel
architecture has three; a 32 bit format, a 64 bit format,
both stored in memory, and an 80 bit register format. The
FPU computational paths may or may not have even more bits
since VLSI designs are often built up from standardized
blocks and it is possible that there are a few unneeded
bits in the least significant block of the matrix that are
easier to include than to edit out. The point I was making
was that any time you stuff a representation with more bits
into a representation with fewer bits, you 'round' the
result in one of the four modes described by the IEEE
floating point standard and that introduces departures from
the 'best' result that have to be accounted for.
Which brings us back to the fact that the patent
description seems to have been obfuscated.
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MTEW[ Reply to This | Parent | # ]
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