|
|
|
| Authored by: Anonymous on Tuesday, January 08 2013 @ 09:34 PM EST |
I might have been a bit too brief in my first message...
> you aren't equating the language used in describing it with the physical
>embodiment other than for implementation verification purposes.
Sorry if it was not clear. I *AM* directly equating the software HDL with the
physical CPU.
The HDL fully defines the CPU, and in combination with the design rules
appropriate for manufacturing process which is sufficient to build an ASIC
implementation. The same process with a different HDL file can generate a USB
controller IC or an Ethernet logic chip or any other similar digital logic
chip.
Synthesis of the net-list for the physical construction is a repeatable and
reliable step; similar to generating the numbers sent to a Computer Controlled
Machine in order to build a physical component from a CAD design; in fact
similar to how procedural software code is compiled and linked to form and
executable binary for a general purpose CPU.
>The sign isn't the referent.
No idea what you meant to say here. Perhaps you could be more concrete?
>Software source code as in the Hardware Description Language used as input
> to a simulator or for synthesizing the CPU design to the transistor and
> wire level is not the CPU itself or programmed cell and interconnects for
> your Field Programmable Gate Array implementation. The HDL source code
>doesn't contain an FPGA. It describes the FPGA's behavior at a programmed
> physical level.
I am not sure what the point is here. No invention referred to in a patent
contains the physical thing the patent refers to. Rather the patent describes
either key attributes of the invention, or how to make the invention.
> The 'invention' is a configured FPGA, assuming that the 'design' is
> novel and useful.
The invention is the CPU, that may be implemented in any number of ways
including an FPGA, an ASIC or perhaps as a simulated CPU on a general purpose
machine.
I agree that it is unlikely that I could invent a CPU that is novel, but if
somebody does invent a novel, non-obvious CPU; then the HDL expression of the
new CPU would be software and perhaps worthy of patent protection.
>Limiting usefulness is any required I/O enabling
> the CPU to transform or reduce to another state any subject
> matter of the patent.
I don't understand this at all.
> There is likewise a lack of novelty in programming
>(configuring) and FPGA.
I did not claim the FPGA configuration mechanism as my invention. I suggested an
FPGA as one of the many potential implementations of the new CPU invention;
where the invention is expressed in the HDL software that defines the CPU
behaviour.
[ Reply to This | Parent | # ]
|
|
|
|
|
