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| Authored by: Anonymous on Thursday, May 10 2012 @ 07:13 PM EDT |
Interpreter only for a start I would assume, JIT can probably come later if they
are willing to put in more resources. That's how bad things are for PPC
nowadays.
For endianness issues, I wonder how does it compare with Sparc and ARM
architectures. I presume Oracle has code that work with those right? Are the
code part of OpenJDK? Or did Sun/Oracle not release them? Is PPC really that
different from Sparc or ARM from an endianness perspective? I thought by now
these architectures were pretty much bi-endian.
As for floating point, I would assume PPC does use IEEE floats. I would also
assume there should be less issues due to most code doing less bit level
manipulation with floating point values (if they do any at all). Also, most of
these bit level manipulation with floating point values tend to eventually end
up using platform specific code (many times even using platform specific
assembly or intrinsic functions instead of standard C) for performance reasons,
so they will most likely need to port them no matter what if there are any. This
is especially true if they target Altivec.[ Reply to This | Parent | # ]
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| Authored by: greed on Thursday, May 10 2012 @ 08:59 PM EDT |
Intel CPUs can use an 80-bit floating point format internally. It's usually
wedged down to a standard 64-bit double for storage. I believe the vector
registers are either 32-bit or 64-bit (float or double in C), but there are so
many revisions of the various SIMD instructions sets I lose track. (MMX, SSE,
3DNow!.)
POWER and PowerPC CPUs use a standard 64-bit IEEE 754 double internally; the
in-memory format and in-register format is the same. POWER2 and later have a
slightly odd 128-bit quad format (long double in C). It works by pairing 64-bit
doubles, and only using the mantissa bits from the low-order one. (One might
expect that all 64 bits of the second register would extend the precision of the
first.)
I can't remember which PowerPC models have quads.
Fun Fact: POWER1 and POWER2 didn't have 32-bit float in the FPU. There were
load/store instructions that would load (store) a 32-bit float to (from) a
64-bit register, but all math was done with all 64 bits.
In all cases, in-memory format on POWER is big-endian, and x86(-64) are
little-endian.
PowerPC is a bi-endian architecture; it can run in little-endian or big-endian
mode. A number of instructions are only available in big-endian mode, though,
so most system builders keep their eggs pointy-side down, like they come from
the store.
(POWER3 and up are really PowerPC models.)
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